Over the previous few a long time, three-dimensional silicon-based supplies have been pivotal to the semiconductor business. Nonetheless, as semiconductor machine know-how has progressed to nodes under 5 nanometers, the business faces elementary challenges in additional miniaturizing transistor dimensions [1], [2]. This miniaturization bottleneck has necessitated the exploration of novel supplies that might doubtlessly supplant silicon. Amongst these, two-dimensional (2D) materials-owing to their atomic-scale thickness-have emerged as promising candidates, primarily as a result of the monolayer construction provides superior electrostatic gate management [3], [4]. This property is especially advantageous for transistors with ultra-short channel lengths, fueling intensive analysis curiosity in each academia and business [5], [6], [7].
In a transistor configuration, the gate electrode, the dielectric layer, and the channel materials collectively type a capacitor, whereby the gate dielectric critically determines the gate voltage modulation of the channel carriers [8]. To harness the inherent gate controllability of 2D channel supplies, it’s crucial to make use of dielectrics with a excessive dielectric fixed (high-k) [9]. Consequently, the event of high-quality high-k dielectric layers on 2D materials surfaces turns into a central problem in realizing high-performance 2D transistors [10], [11], [12].
The standard of high-k dielectric/2D materials channel heterostructure is predominantly restricted by the high-k dielectric formation course of on 2D supplies. Typical methods for depositing high-k movies onto 3D substrates (e.g., silicon) embrace chemical vapor deposition, atomic layer deposition, electron beam or thermal evaporation, and magnetron sputtering [13], [14], [15]. Nonetheless, when instantly utilized to 2D supplies, these processes usually fail to attain high-quality interfaces. The important thing hurdle lies within the shortage of dangling bonds on 2D surfaces, that are important for nucleation of dielectric movies [16]. Consequently, dielectric supplies are inclined to type island-like constructions with excessive defect densities on the dielectric/channel interface, considerably degrading machine efficiency [17].
To handle these challenges, researchers have proposed varied methods. Early makes an attempt concerned floor functionalization or pre-deposition therapies of 2D supplies to extend nucleation websites [18]. Though these approaches can promote uniform movie formation, they danger disrupting the atomic-scale lattice integrity of 2D crystals and will induce unintended doping, rendering {the electrical} transport traits (e.g. threshold voltage) unpredictable [19]. The “seed layer” methods have been developed to allow the deposition of ultrathin high-k supplies like HfO2 on 2D channels [20], however seed layers themselves could introduce contamination or exhibit suboptimal dielectric properties, thus compromising machine efficiency.
Layered 2D dielectric supplies, corresponding to GdOCl, Bi2SeO5, and Bi2SiO5, have garnered important consideration [10], [11], [12], [13]. Mechanical exfoliation and switch of 2D dielectrics onto 2D materials channels can obtain vdW heterostructures with atomically clear interfaces [12], thereby bettering machine reliability and efficiency [3], [4]. Bi2SeO5 and Bi2SiO5 exhibit excessive dielectric constants increased than 23, however small bandgaps of ∼3.5 eV. GdOCl supplies possess bigger bandgaps ∼4.2 eV, however their dielectric constants are comparatively low. Lately, Ga2O3 was demonstrated as a high-quality gate dielectric for 2D transistors [21], however it’s synthesized with a manually managed liquid-phase deposition methodology, limiting its potential for scalable integration.
Layered GaPS4 has not too long ago emerged as a promising high-k dielectric for two-dimensional (2D) field-effect transistors (FETs) [22]. In comparison with the GaPS4 supplies (99.9 % purity) within the prior research [22], which demonstrated a dielectric fixed round 5, our high-purity (99.9995 %) GaPS4 crystals present a excessive dielectric fixed (as much as 35) and consequently an ultra-scaled equal oxide thickness (EOT) of 1.0 nm in MoS2 FETs. Ultraviolet-visible (UV–vis) absorption spectra of GaPS4 reveal a bandgap of bigger than 4.15 eV, and electrical measurements set up a excessive dielectric fixed of 35. Theoretical calculations point out a unipolar-like barrier within the MoS2/GaPS4 heterostructure for electrons with an power of 1.92 eV, suggesting the potential machine software of this heterostructure in unipolar barrier photodetectors [23]. When GaPS4 is employed because the gate dielectric in MoS2 FETs, the units exhibit a low leakage present (Ig) suppressed to 10−13 A, a minimal hysteresis of ∼20 mV, and a excessive on/off present ratio of three × 108. These superior properties are attributed to the dangling-bond-free, atomically easy floor of GaPS4, which facilitates a vdW interface and ensures glorious compatibility with 2D semiconductor supplies.
