Quantum error correction on a hexagonal lattice
In our Willow structure, every bodily qubit is linked to its 4 nearest neighbors, forming a sq. lattice. This association of connections permits gates between the neighboring qubits, but additionally introduces design constraints, such because the overhead of additional wires wanted to manage couplers between qubits. Realizing error correction as an alternative on a hexagonal lattice would allow every qubit to attach with solely three neighbors as an alternative of 4, thereby simplifying the design and fabrication course of of those giant chips and enhancing {hardware} efficiency.
To realize error correction with solely three couplers per qubit, we make use of dynamic circuits that characteristic two distinct varieties of error correction cycles. Each cycle varieties leverage three couplers per qubit, with one coupler utilized twice throughout the cycle. The result’s a quantum error correction circuit with dynamic, overlapping detecting areas that may nonetheless be used to triangulate errors, however solely requiring three couplers per qubit.
We evaluated this three-coupler error correction circuit on our Willow processor, which has sq. connectivity. To measure the hexagonal code, we turned off all of the unused couplers, to simulate the efficiency of hexagonal connectivity. We discovered that because the code’s distance scales from 3 to five, the logical error price improves by an element of two.15, matching the efficiency of a conventional static circuit working on the identical {hardware} that we offered in our milestone experiment final yr.
Our findings show the feasibility of developing a hexagonal qubit lattice for quantum error correction, a design house we completely investigated in simulation. By adopting a hexagonal lattice, we will considerably cut back the complexity of our optimization algorithms for choosing qubit and gate frequencies. This simplification results in a 15% enchancment within the simulated error suppression issue, showcasing the novel capabilities unlocked by designing a processor with three couplers per qubit, relatively than 4.
